Automatic conditional cross-connection

ABSTRACT

A cross-connect having a cross-connecting processor, data memory for storing cross-connection data in cyclically recurring elements, and a control memory for storing instructions controlling the cross-connecting. The cross-connect further having a condition monitoring block arranged so as to selectively read cross-connection data from the data memory and indicate the status of a certain cyclically recurring bit or bit combination. In response to the reading of a certain instruction from the control memory the cross-connecting processor reads certain cross-connection data from a certain first source if the condition monitoring block has indicated that a certain cyclically recurring bit or bit combination is in a predetermined first state, and from a certain second if the condition monitoring block has indicated that the cyclically recurring bit or bit combination is in a predetermined second state.

PRIORITY CLAIM

This is a national stage of PCT application No. PCT/FI98/00659, filed onAug. 26, 1998. Priority is claimed on that application, and on patentapplication Ser. No. 973,506 filed in Finland on Aug. 26, 1997.

The invention relates in general to cross-connects which have interfacesto an external communications system, said interfaces being controlledby an internal control circuit in the cross-connect. In particular theinvention relates to devices of said nature, in which the operation ofthe control circuit depends on whether the connections with the externalcommunications system are functioning faultlessly.

FIG. 1a shows a base station network in a cellular radio system,comprising a base station controller 100 (BSC) and a plurality of basetransceiver stations 101 (BTS). The base station controller 100 isfurther connected to a mobile switching center, which is not shown. Toenable transmission of data between them, the base station controller100 and base transceiver stations 101 are interlinked through aplurality of connections which constitute a so-called transmissionsystem in the base station network. The standards for a cellular radiosystem such as the Global System for Mobile Telecommunications (GSM),for example, usually do not specify the transmission method to be usedin the base station network, except for defining the functions that thetransmission method has to be capable to realize. In GSM, the interfacebetween two base transceiver stations or a base transceiver station andthe base station controller, as defined in the standards, is called theAbis interface. The transmission method may comprise e.g. a 2-Mbit/s or1.5-Mbit/s PCM connection (Pulse Coded Modulation; ITU-T G.703 andG.704), SDH connection (Synchronous Digital Hierarchy; ITU-T G.774.03),ATM connection (Asynchronous Transfer Mode; ETS 300 371), ISDNconnection (Integrated Services Digital Network), or a HDSL connection(High Density Digital Subscriber Line). The physical connection maycomprise an ordinary copper wire, optical cable or a microwave radiolink.

In the base transceiver stations and base station controller of thesystem depicted in FIG. 1a connection to the transmission system isrealized through a cross-connect 102. A cross-connect 102 in a basetransceiver station may comprise one or more transmission units (TRU).Cross-connecting means that the incoming data, which are arranged inframes, can be connected to the outgoing direction in thecross-connecting device such that the location of the data bits in theframes can be altered. The base transceiver station cross-connect“drops” certain bits and time slots in the transmission system frame tothe base transceiver station, i.e. directs data concerning thatparticular base transceiver station, which arrive in certain time slots,to the base transceiver station and, on the other hand, associates thedata leaving the base transceiver station in the direction of the basestation controller with certain time slots allocated to that basetransceiver station. The cross-connect may also perform summing,multiplication or other operations on the incoming data before the dataare connected to the outgoing direction. When the cross-connect isplaced either in the same equipment rack with the base transceiverstation or in its immediate vicinity, the base transceiver stationconstitutes a compact unit and the base station network can be easilymodified and expanded.

The transmission capacity allocated to one base transceiver stationdepends on how many TRX (Transmit/Receive) units 103 it contains. TheTRXs constitute a radio interface to terminal equipment 104, and thenumber of TRX units determines how many simultaneous speech or dataconnections the base transceiver station can handle. Different parts ofthe base station network may also require different amounts oftransmission capacity depending on the base station network topology. Ina tree-like base station network the highest capacity is required ofconnections near to the base station controller.

At its simplest a transmission system comprises a so-calledpoint-to-point connection where a given GSM base transceiver stationcommunicates directly with the base station controller and through thelatter with a switching center. However, in the case of a 2-Mbit/s PCM,for example, the traffic capacity required by a base transceiver stationhaving one TRX is quite small compared to the whole transmission band.Typically, two and a half time slots in a PCM frame (6 to 8 voicechannels and signalling), or 160 kbit/s, are reserved for one TRX.Therefore, a point-to-point connection often wastes capacity and becomesexpensive. On the other hand, the use of existing ISDN connections forpoint-to-point connections may be an alluring idea. Network back-up canbe realized using redundant point-to-point connections.

The transmission band can be utilized more efficiently by chaining basetransceiver stations (so-called multidrop chain structure). In thechain, several base transceiver stations share, on a time divisionbasis, the same transmission medium, thus better utilizing theconnection capacity. Thus the integrated cross-connecting function inthe base transceiver station really becomes useful as the time slotarrangements can be made within the base transceiver station.

Loop networks are used for network duplication. Base transceiverstations are looped together so that there exists at all times atransmission connection in both directions of the loop from each basetransceiver station to the BSC. Normally, one of the connections isactive. Network monitoring is realized using status bits, or so-calledcalled pilot bits, which each base transceiver station sends in bothtransmission directions in the loop. A change in the state of a pilotbit indicates a network fault, at which point cross-connects in basetransceiver stations switch over to the back-up connection. Networksynchronization data are also sent using status bits of their own. Aswitch-over as quick as possible enables network operation withoutdisconnected calls even in fault situations. A GSM call can tolerate a500-ms break in the transmission connection without disconnecting thecall proper.

FIG. 1b shows a prior-art cross-connect in a GSM base transceiverstation. It has two separate transmission units 110 and 111. Bothtransmission units have an “out-bound” Abis interface according to theGSM standards, i.e. an interface to either the base station controlleror another base transceiver station (not shown). In addition, bothtransmission units have an administrative connection to the base stationcontroller. One of the transmission units is also connected to theinternal data bus in the base transceiver station which is used insending the downlink data associated with the voice and signallingconnections handled by the base transceiver station to the TRX units(not shown) of the base transceiver station, and, correspondingly, theuplink data from the TRX units to the base station controller. In theprior-art implementation the transmission units 110 and 111 in thecross-connect are wholly separate and they both have internalcross-connecting buses of their own. The transmission units areinterconnected through the Abis interface as shown in FIG. 1b.

In future cellular radio systems the average cell size will be smallerand, hence, the number of cells greater than today so that transmissionsystems shall be capable of handling more base transceiver stations, andnetwork topologies and cross-connections will be more complex than now.The operator providing the transmission medium will not necessarily bethe same as the operator running the cellular radio system, so thelatter must be able to realize transmission between base transceiverstations and base station controllers as advantageously and efficientlyas possible, using the various transmission possibilities available.

SUMMARY OF THE INVENTION

An object of this invention is to provide a base transceiver stationcross-connect which responds to transmission system faults quickly,effectively and reliably.

The objects of the invention are achieved by realizing in thecross-connect hardware-based monitoring of transmission system statusbits and cross-connect changes on the basis of changes observed in thestate of the status bits.

The cross-connect according to the invention comprises across-connecting processor, data memory for storing cross-connectiondata in cyclically recurring elements, and a control memory for storinginstructions controlling the cross-connecting. It is characterized inthat

it comprises a condition monitoring block arranged so as to selectivelyread cross-connection data from said data memory and indicate a changein the status of a certain cyclically recurring bit or bit combination,and

said cross-connecting processor is arranged so as to perform, inresponse to the reading of a certain instruction from said controlmemory, a certain first switching operation to certain cross-connectiondata when said condition monitoring block has indicated that saidcyclically recurring bit or bit combination is in a predetermined firststate, and a certain second switching operation to said cross-connectiondata when said condition monitoring block has indicated that saidcyclically recurring bit or bit combination is in a predetermined secondstate.

The invention is also directed to a method for realizing conditionalcross-connection. The method according to the invention is characterizedin that it comprises steps in which

a) a certain portion of the cross-connection data stored in the datamemory is read and its status is indicated,

b) a conditional cross-connecting instruction, which containsinformation on at least two cross-connection data sources, is read fromthe control memory, and

c) if a predetermined first status was indicated in step a), a certainfirst switching operation is performed to certain cross-connection datathe source of which is specified in the cross-connecting instruction,and

d) if a predetermined second status was indicated in step a), a certainsecond switching operation is performed to certain cross-connection datathe source of which is specified in the cross-connecting instruction.

In the inventional structural solution the cross-connection and thefunctions required by the transmission connections are implementedmodularly by decentralizing them into several parts which in this patentapplication are called transmission units. Decentralization is to beunderstood such that a single transmission unit can establish alltransmission connections of a base transceiver station but units can beadded according to capacity requirements so that they function as awhole. The cross-connection is shared by the transmission units througha parallel bus in the so-called motherboard, which bus interconnects thetransmission units and is advantageously duplicated for reliability.From the point of view of base station control the transmission unitsconstitute one controllable whole. Each transmission unit realizes acertain type of standard transmission interface.

As the amount of GSM traffic increases there also emerges a need to havedifferent transmission interfaces in one and the same base transceiverstation. Therefore, the new base station solution can use transmissionunits of many different types. Within a transmission unit, a given firstpart realizes the transmission interface and converts the received data,which are to be cross-connected, from the format used in thetransmission system to the internal format used in the cross-connect.The data are written in that format to the cross-connecting businterconnecting the transmission units. The other parts of thetransmission unit realize advantageously at least cross-connection, unitcontrol, synchronization with other transmission units and interfaces tothe base station motherboard. A transmission unit may comprise one ormore printed circuit boards. Hereinafter, the term “special part” refersto parts realizing a transmission interface and the term “common part”refers to the cross-connecting and bus interface block. In addition tothe functions mentioned above, a transmission unit may include otherfunctional blocks, too.

The special part in the transmission unit adapts the cross-connect inthe base transceiver station to the base station network's transmissionsystem, which may be a PCM, HDSL or ISDN system, for example.Advantageously the special part may also comprise adapter circuits fordifferent physical transmission media such as copper wire, optical cableor radio link.

In the common part, all data traveling through the cross-connecting busare stored in the data memory. One of the blocks in the cross-connectingcircuit in the common part is the condition monitoring block whichreads, in accordance with pre-set conditions, certain pilot bits fromthe data stored in the data memory. A change in the state of a pilot bitimplies a fault in the transmission system, whereby the state of thestatus register in the condition monitoring block changes. Theinstructions controlling the operation of the cross-connecting processortake into account the situations in which the operation depends on thestatus register bits. As the cross-connecting processor, controlled byan instruction, detects a change in the status register, it carries outthe cross-connecting action defined by the instruction in a differentmanner than if no changes had been detected in the status register.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail with reference to thepreferred embodiments presented by way of example and to theaccompanying drawings wherein

FIG. 1a shows a known base station network,

FIG. 1b shows a known cross-connect in a base transceiver station,

FIG. 2 shows a cross-connect in which the invention can be applied,

FIG. 3 shows in more detail part of FIG. 2,

FIG. 4 shows in more detail another part of FIG. 2, and

FIG. 5 shows in more detail part of FIG. 4.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

FIG. 2 shows an example of the new structure for the cross-connect in abase transceiver station. The cross-connect comprises at least onetransmission unit 200. It may also have more transmission unitsdepending on the desired quality and quantity of the transmissionconnections. Each transmission unit 200 comprises a common part 202 andspecial part 204. In a preferred embodiment each transmission unit isrealized on a circuit board containing the necessary physical interfacesand functional blocks required by the common part 202 and special part204. The transmission units are electrically coupled to the internaldoubled cross-connecting bus of the base transceiver station. Thetransmission units may also be coupled to the data bus used by thetransmitter/receiver units, or TRXs, of the base transceiver station. Ina typical embodiment, where the TRX units of the base transceiverstation are connected to the data bus, at least one transmission unithas to be coupled to the data bus to enable data communications betweenthe TRX units and transmission connections outside the base transceiverstation via the transmission units. In other embodiments of theinvention the TRX units may also be coupled to the cross-connecting bus.

In addition to the cross-connecting bus and data bus shown in FIG. 2 thebase transceiver station may also include other buses for controllingand synchronizing the operation of the transmission units. In such anembodiment the transmission units are coupled to those buses, too.

The special part 204 in each transmission unit 200 has at least onebi-directional external transmission connection 206 which may be e.g. aPCM, SDH, ATM, ISDN, HDSL or some other connection. The special part,which is of RRI (Radio Relay Interface) type, is advantageously directlyconnected to the outside unit of the microwave radio in the basetransceiver station. In one cross-connect the external transmissionconnections in the special parts of the transmission units may all beidentical or they may be different. In addition, a transmission unit mayhave interfaces for two or more types of transmission connections. Datatraffic between the special part 204 and common part 202 is preferablysubstantially similar in all transmission units independent of the typeof the external transmission connection. An advantageous solution is toprovide N standard-capacity (say, 2.048 Mbit/s) connections between thespecial part and common part, where N is chosen such that thetransmission capacity between the special part and common part at leastequals the combined capacities of the transmission connections coupledto the special part.

FIG. 3 shows in more detail a special part 300 of a transmission unit ina cross-connect according to the invention, which special part isintended for the transmission and reception of a PCM signal. It has anN-channel line interface circuit 301 which, when receiving, is adaptedto the received signal level and extracts and regenerates timinginformation from the data. Depending on the application, the lineimpedance may be 75 ohms, 120 ohms (E1) or 100 ohms (T1). Whentransmitting, the line interface circuit 301 adapts the data to thetransmission medium, which is a coaxial cable or twisted-wire pair. Thetransmission line is logically terminated by an N-channel framer circuit303. When receiving, it decodes the line coding (e.g. high densitybipolar 3, HDB3; alternate mark inversion, AMI; or binary 8 zerosubstitution, B8ZS) and becomes locked to the frame phase by means offrame alignment words in the data stream. In addition, the framercircuit 303 includes other functions e.g. for processing overhead data;decoding the channel signalling, handling of T1 HDLC messages,processing various alarm information, etc. Finally, the special partdelivers the data stream to the common part in a form in which the clocksignal is separate from the data and the start of a frame is indicatedusing a signal of its own. In the outgoing direction the steps mentionedabove are carried out in the reverse order.

Regardless of whether the transmission interface capacity is 2.048Mbit/s (E1) or 1.554 Mbit/s (T1), the framer circuit 303 always providesan N×2.048 Mbit/s interface to the common part. This is achieved byinternal data buffering inside the framer circuit 303 and by placing thedata in the E1 frame structure in connections between the framer circuit303 and common part 202, so that if the lower-capacity T1 framestructure is used in the transmission, the “extra” time slots in the E1frame structure are filled with pseudo-data. The same principle holdswith other applications of the special part; the interface to the commonpart is always N×2.048 Mbit/s.

FIG. 4 shows in simplified form the basic electrical structure of atransmission unit's common part 202. The common part comprises across-connecting circuit 231, which usually is an application specificintegrated circuit (ASIC) and which hereinafter will be called aswitching circuit. In addition, the common part comprises an oscillator232, microprocessor 233 and a cross-connecting bus interface 234.Transmitter and receiver blocks 235 a and 235 b for communications withthe special part are located in the switching circuit 231 which furthercomprises, among other things, a cross-connecting processor 236, datamemory (DM) 237 and control memory (CM) 238. The data memory 237 servesas an intermediate data store where the outgoing data, i.e. data flowingfrom the cross-connecting bus to transmitter blocks via the switchingcircuit, are temporarily stored for rearrangement. The microprocessor233 controls the operation of the entire common part.

Through the cross-connecting bus interface 234 the common part isconnected to the cross-connect's cross-connecting bus whose datastructure conforms to a certain bus protocol. Data on thecross-connecting bus are arranged in frames having a certain regularform. Each frame on the cross-connecting bus is stored in its turn tothe data memory DM of the cross-connecting circuit 231. Across-connecting processor XC reads data from the data memory DM e.g.one byte at a time and writes those data to transmitter blocks 235 awhich lead to the special part of the transmission unit. A term calledgranularity defines the smallest amount of data that can beindependently managed in a write operation. If the granularity is onebit, it means that each bit read from the data memory DM and written totransmitter blocks 235 a can be controlled independent of other bits.Instruction words read from the control memory CM determine the order inwhich the data read from the data memory DM are written to transmitterblocks 235 a.

A GSM call according to the prior art requires a 16-kbit/s capacity inthe transmission system, corresponding to two bits in a PCM transmissionsystem frame (according to G.703 and G.704 standards, PCM frames arerepeated 8000 times a second in the transmission system so that one bitper frame corresponds to a capacity of 8 kbit/s). However, in thecross-connect according to the invention it is advantageous to preparefor the so-called half-rate GSM connections, each of which represents atransmission capacity of just 8 kbit/s. Since cross-connects have to beable to handle these connections independent of each other and,furthermore, since it is advantageous to prepare for the channelassociated signalling (CAS) according to standards G.703 and G.704 incross-connects. the granularity has to be one bit.

To provide background for the invention it will be next describedbriefly various switching types in a cross-connect. The B type is thesimplest switching type: for each outbound bit it is possible toindicate the position from which the bit is to be connected. Ifgranularity is one bit and the transmission connection complies withG.703/G.704, the cross-connecting level is 8 kbit/s. If theaforementioned channel associated signalling (CAS) is used, theswitching circuit may cross-connect it. too, by specifying a 64-kbit/sconnection in the time slot corresponding to the CAS channel. Althoughthe switching circuit according to the invention will probably be usedprimarily in GSM systems in which CAS is not used, it is advantageous tosupport the cross-connection of CAS in the switching circuit in order toprepare for a situation in which the GSM base station system is part ofa fixed network and the fixed network channels with CAS signalling mustbe connected through.

The Y type can be used for specifying conditional switching. Granularitymay be 32 kbit/s or 64 kbit/s, depending on whether the CAS, too, is tobe switched. Conditional switching means that a certain outboundinformation element (bit, portion of byte or byte) can be connected fromtwo alternative sources, i.e. two alternative locations in the incomingdata. Y-type switching is used e.g. at a loop network base station whichin principle receives the same information from two different directionsvia the transmission system. In that case the cross-connect in the basestation chooses one of the received data to be transmitted further (orto be sent to the TRX unit in the base station). The data source ischanged when a certain condition is met. The existence andimplementation of conditional switching as such are known but thepresent invention pertains to how the cross-connect decides that theconditional switching condition is met and the connection should bechanged.

C-type switching can be used for carrying out digital summing ofchannels. Depending on the number of sources to be summed and whether ornot CAS channels are to be summed the switching level may be 16 kbit/s,32 kbit/s or 64 kbit/s. Determining the sources to be summed andinstructions controlling the summing are described in more detail inpatent application “Instruction architecture of cross-connectingprocessor” filed at the same time with this application by the sameapplicant.

FIG. 5 shows a simplified diagram of a switching circuit in across-connect according to the invention. For simplicity, only some ofthe blocks in the switching circuit are shown. Receiver blocks 501-508receive data from the special part (not shown) of a transmission unitand transmit the data through a kind of buffer storage arrangement 509to a cross-connecting bus interface 510. The latter writes the receiveddata to the cross-connecting bus, to a location in the frame structureof the cross-connecting bus that is allocated to the transmission unitin question. All data read from the cross-connecting bus are stored inframes in the data memory 511 from where they can be read by thecross-connecting processor 512, switching circuit's microprocessorinterface 513 and the condition monitoring block 514. Reading is carriedout through read ports of which there are two in the data memory 511.One read port 515 is used solely by the cross-connecting processor 512because in this exemplary case it has to read data from the data memoryat every clock edge of the switching circuit's 16.384-MHz clockfrequency signal. The use of the other read port 516 is time sharedbetween the microprocessor interface 513 and condition monitoring block514 in such a manner that the condition monitoring block has the rightof precedence to the read port 516.

Between the microprocessor interface 513 and condition monitoring block514 there is a read and write connection through which a microprocessor,which is coupled to the microprocessor interface 513 and controls theoperation of the transmission unit in question, can read the contents ofmemory locations in the condition monitoring block 514 and write tothose locations. In addition, there is a read connection between thecondition monitoring block 514 and cross-connecting processor 512through which the cross-connecting processor 512 can read the contentsof memory locations in the condition monitoring block 514. The conditionmonitoring block can store a certain number of conditions in it so thatdata on the cross-connecting bus can be monitored in regard to thoseconditions. Lest the condition monitoring block become unreasonably big,the number of conditions should be limited. A suitable upper limit is128 conditions.

A condition comprises a bit address, definition register and a conditionstatus register. In addition, there has to be a certain counter for eachcondition. The bit address identifies the bit in the cross-connectingbus frame structure that is to be monitored. The length of the bitaddress is thus determined by the number of bits in the cross-connectingbus frame structure; in the development work that led to the inventionit was used a cross-connecting bus frame that comprised 13,824 bits (54blocks with 32 time slots each and 8 bits in each time slot), in whichcase the bit address length has to be 14 bits (2¹⁴=16,384). Thedefinition register uses certain code values to specify special featuresrelated to the processing of each condition. A definition register valuemay e.g. specify whether the condition in question is updated by theswitching circuit or a microprocessor coupled to the microprocessorinterface, where “updating” means that the switching circuit ormicroprocessor monitors the bit indicated by the condition and, whennecessary, responds to a change detected in the status of the bit. Acertain code value in the definition register may also indicate whetherthe bit monitored is normal data, Sa bit (a certain national usage bitin the zero time slot in the G.703/G.704 E1 frame) or a CAS signallingbit (a certain channel associated signalling bit in the G.703/G.704 E1frame), and what is the degree of filtering directed to the bit inquestion. The size of the definition register may be four bits percondition, for example.

In a preferred embodiment the size of the condition status register ofeach condition is just one bit, and its value indicates the bit's“established status” detected in the position specified by the bitaddress. In this context, “established” means that the value of thecondition status register is not changed until a value other than thatin the condition status register has been detected N times insuccession. Number N indicates the degree of filtering. Acondition-specific counter is needed to count how many deviating bitvalues have been detected in succession before the value in thecondition status register is changed.

By means of the condition monitoring block 514 the switching circuit canindependently monitor the status of data bits coming in through anycross-connect interface in the base station. Monitoring takes place onlyafter the cross-connecting bus, which makes possible the monitoring ofdata coming in through other transmission units in the cross-connect aswell.

By means of the bit address any condition can be directed to any timeslot and bit in any cross-connecting bus frame block. In addition, it ispossible to set monitoring for the Sa bits and CAS bits in odd-numberedframes. Each bit can be monitored using either three- or six-stagefiltering, i.e. the status information is not changed until the changedbit status has been detected three or six times in succession.

There are two main uses for bit monitoring in a transmission unit.First, pilot bit status data are used as Y-type switching conditions. Inthe duplication of a loop base station network the cross-connect thatcarries out Y-type switching is set so as to monitor pilot bits in bothtransmission directions. Normally, when the transmission connections arefunctioning faultlessly, the value of the pilot bit under observationarrives in the monitoring cross-connect identical from both transmissiondirections so that the cross-connect selects for switching the datacoming from either one of the transmission directions. The selection isconservative, i.e. the cross-connect prefers to select the transmissiondirection that was already in use. If the status of a pilot bit comingfrom the chosen transmission direction changes but the value of the samebit coming from the alternative transmission direction remainsunchanged, the cross-connect starts to connect data coming from the“standby” transmission direction. Since the monitoring of the status ofpilot bits is an integral part of the operation of the switchingcircuit, the switch-over can be carried out very quickly as the pilotbit status information changes. It should be noted that, because offiltering, a change in the value of a pilot bit is not the same thing asa change in the corresponding status information; three- or six-stagefiltering is used lest single bit errors on the transmission path makethe connection oscillate.

Second, bit monitoring realized at the switching circuit's hardwarelevel can be utilized in the fast synchronization source switch-overbased on the monitoring of synchronization bits in a loop or chainnetwork. So-called master clock bit (MCB) and loop clock bit (LCB)determine the loop input interface, to which synchronization isrealized, and whether or not to operate as the master clock of thesystem. In practice, the switching circuit is set so as to monitorsynchronization bits and it sends an interrupt to the microprocessor ifthe status information of the synchronization bits is changed. Afterthat, the microprocessor reads the status information from the switchingcircuit and possibly carries out synchronization source switch-over.Six-stage filtering may also be used in that case. The bit monitoringfunction in the switching circuit can also be used in situations whereit is desirable to monitor fixed status information in the data bits.

Monitoring of pilot bits and MCB/LCB bits in cross-connects hasconventionally been realized at software level using the pollingprinciple and software filtering. This has considerably added to themicroprocessor load in cases which have many Y-type connectionsassociated with different conditions. Thus, bit monitoring realized bythe switching circuit considerably reduces the load of themicroprocessor. A second advantage is that in Y-type connections thesource switch-over is performed with a very short delay, even in lessthan 400 μs. Likewise, the MCB/LCB status information is detectedquickly by the processor because of the interrupt request generated forit.

If the maximum amount of conditions is 128 and the length of the bitaddress is 14 bits, the size of the condition source RAM, i.e. the RAMthat contains the bit addresses, is 128×14=1792 bits. The bitdefinitions are advantageously realized in RAM because it would take upto 50,000 logic gates to realize a storage of this size by registers.

Conditions are read cyclically in phase with the cross-connecting busframe so that all 128 monitoring occurrences are spread evenly acrossthe cross-connecting bus frame time (say, 125 μs). A monitoring cycleadvantageously utilizes the block and time slot counters of thecross-connecting bus. For each condition, a bit address and the contentsof the definition register are first read. If the condition is an updateby the microprocessor, defined in the definition register, the conditionmonitoring block will do nothing more. Update by microprocessor is usedfor Y-type connections that comply with a condition transparent to theswitching circuit. If the bit monitored is normal data or an Sa bit, thecontents of the condition source RAM are read each time, and in the caseof CAS, every 16th time. CAS visible to the switching circuit is alwaysfixed for the duration of 16 frames. After that, the data RAM is read ata memory location indicated by the condition source RAM. If thedefinition was Sa bit, bit 2 is interpreted to find out whether theframe is an even-numbered one, in which case it is rejected.

When the bit monitored has been read from the data RAM, its status iscompared with the value in the condition status register. If the valuesmatch, no further measures are taken. If the values differ, the value ofthe so-called condition filtering RAM is read for the condition inquestion. This value is increased by one unless it already has themaximum value, in which case it becomes one. The maximum value dependson whether three- or six-stage filtering is used. If the value of thefiltering RAM is 2 (or 5 in the case of six-stage filtering), it isfurther increased by one, but also the value of the condition statusregister is changed. Thus, the value of the condition status registerassociated with the condition is not changed immediately but only afterthe status of the bit monitored will have been changed for three or sixsuccessive cycles. So, to realize six-stage filtering, a 3×128-bit RAMis needed as condition filtering memory.

Above it was described how the condition status register value dependson read operations carried out by the condition monitoring block. Theconditional cross-connection proper takes place when thecross-connecting processor reads from the control memory an instructionwhich is of the so-called Y type, i.e. defines for a certain outboundbyte or portion of byte at least two alternative sources (i.e. locationsof byte or portion of byte in the frame structure read from thecross-connecting bus) and at least one condition associated with acondition status register whose value determines which source isconnected to the outbound byte or portion of byte. The structure of theY-type instruction is described in more detail in patent application“Instruction architecture of cross-connecting processor” filed at thesame time with this application by the same applicant. Its essentialparts include the type identifier, which tells that this is a Y-typeinstruction, location identifiers, which indicate the position of thealternative data sources in the frame stored in the data memory, andcondition identifiers, which indicate the condition(s) that affect theY-type connection in question. The instruction may also contain fixeddata, or a bit pattern written into the outbound byte or portion of byteinstead of the bit pattern read from the data memory upon a certainvalue of the condition(s). The instruction may also specify that acertain value of the condition(s) causes a logical operation between thebit pattern read from the data memory and the fixed data included in theinstruction. The address in the control memory of the instructiondetermines the transmitter interface and time slot that are affected bythe conditional cross-connection in question.

In accordance with the inventional idea disclosed in this patentapplication the condition monitoring block may also monitor, instead ofa single bit, a multibit combination such as portion of a byte, byte oreven several bytes. If, however, one wants to monitor all bits in a bitcombination simultaneously, the condition status register has to bebigger than described above, since the condition status register musthave a status bit for each bit monitored. This adds to the complexity ofthe switching circuit needed. An alternative way of monitoring severalbits is to perform a simple logic operation on the bits monitored, theresult of said operation being one bit or, in the case of a great numberof bits monitored, a considerably smaller number of bits. The result ofthe logic operation is compared with a condition status register valueof equal bit size in the same way that one monitored bit was abovecompared with the one-bit value of the condition status register.

Embodiments of the invention may of course vary within the scope of theclaims set forth below. For example, the invention does not require thatcross-connection data be stored in the data memory in frames. To realizecondition monitoring it suffices that data are stored with cyclicrecurrence, i.e. each bit or bit combination monitored occurs in thedata memory with such regularity that the condition monitoring block candirect its read operation to them always when they occur or at leastonce in a while. Naturally, the more often the condition monitoringblock reads a bit or bit combination, the more quickly a change in thestatus of the bit or bit combination is detected.

What is claimed is:
 1. A cross-connect comprising: a cross-connectingprocessor; data memory for storing cross-connection data in cyclicallyrecurring elements; a control memory for storing instructionscontrolling the cross-connection; and a condition monitoring blockarranged so as to selectively read cross-connection data from said datamemory and indicate the status of a certain cyclically recurring bit orbit combination, said cross-connecting processor being arranged so as topreform, in response to the reading of a certain instruction from saidcontrol memory, a certain first switching operation to certaincross-connection data when said condition monitoring block has indicatedthat said cyclically recurring bit or bit combination is in apredetermined first state, and a certain second switching operation tosaid cross-connection data when said condition monitoring block hasindicated that said cyclically recurring bit or bit combination is in apredetermined second state.
 2. The cross-connect of claim 1, whereinsaid data memory is arranged so as to store cross-connection data inframes, and said condition monitoring block is arranged so as to read acertain bit in every frame stored in the data memory.
 3. Thecross-connect of claim 2, wherein said condition monitoring blockcomprises a condition status register for storing the value of a certainbit in a frame read from the data memory, and said condition monitoringblock is arranged so as to indicate a change in the status of the bit inquestion in response to having detected that the bit value in Nsuccessive frames stored in the data memory differs from the valuestored in said condition status register, where N is a positive integer,so that said condition monitoring block is also arranged so as to storethe new value of the bit in question in the condition status registeronly after it has remained unchanged for N successive frames.
 4. Thecross-connect of claim 1, wherein said first and second switchingoperations are defined in relation to a first data source and a seconddata source which are locations in the cyclically recurring elementstored in said data memory and said cross-connecting processor isarranged so as to read the addresses of said first source and saidsecond source from said instruction.
 5. The cross-connect of claim 1,further comprising a processor interface to provide a communicationsconnection with a microprocessor so that the selective read operationsperformed by said condition monitoring block can be controlled by amicroprocessor coupled to said processor interface.
 6. A method forrealizing conditional cross-connection in a cross-connect whichcomprises a cross-connecting processor, data memory for storingcross-connection data in cyclically recurring elements, and a controlmemory for storing instructions controlling the cross-connectingcomprising: a) a certain portion of the cross-connection data stored inthe data memory is read and a status of the data is indicated, b) aconditional cross-connecting instruction, which contains information onat least two cross-connection data sources, is read from the controlmemory, and c) if a predetermined first status was indicated in step a),a certain first switching operation is performed to certaincross-connection data the source of which is specified in thecross-connecting instruction, and d) if a predetermined second statuswas indicated in step a), a certain second switching operation isperformed to certain cross-connection data the source of which isspecified in the cross-connecting instruction.
 7. The method of claim 6,wherein step a) is repeated N times where N is a positive integer,keeping the value of the portion of cross-connection data stored earlierin the data memory, unchanged, and status change is indicated in step a)only if the value of the portion of the data read differs in all Nreadings from the value of the portion of the cross-connection datastored earlier in the data memory.
 8. A base station network in acellular radio system, comprising: a: base station controller; at leastone base station; a transmission system linking together the basestation controller and the at least one base station; and across-connect in at least one base station, the cross-connectcomprising: a cross-connecting processor; data memory for storingcross-connection data in cyclically recurring elements; a control memoryfor storing instructions controlling the cross-connection; and acondition monitoring block arranged so as to selectively readcross-connection data from said data memory and indicate the status of acertain cyclically recurring bit or bit combination, saidcross-connecting processor being arranged so as to perform, in responseto the reading of a certain instruction from said control memory, acertain first switching operation to certain cross-connection data whensaid condition monitoring block has indicated that said cyclicallyrecurring bit or bit combination is in a predetermined first state, anda certain second switching operation to said cross-connection data whensaid condition monitoring block has indicated that said cyclicallyrecurring bit or bit combination is in a predetermined second state. 9.The cellular base station network of claim 8, wherein the cellular basestation network has a loop-like topology so that said base station hastwo transmission connections and the cross-connect is arranged so as toselect one of said two transmission connections as the source ofcross-connection data using conditional cross-connecting.